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TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
PARAMETER MEASUREMENT INFORMATION (CONTINUED)  
timing parameters and board routing analysis  
The timing parameter values specified in this data sheet do not include delays by board routings. As a good  
board design practice, such delays must always be taken into account. Timing values may be adjusted by  
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification  
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate  
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature  
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing  
differences.  
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and  
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,  
but also tends to improve the input hold time margins (see Table 33 and Figure 15).  
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents  
board route delays and how they are perceived by the DSP and the external device.  
Table 33. Board-Level Parameters Example (see Figure 15)  
NO.  
1
DESCRIPTION  
Clock route delay  
2
Minimum DSP hold time  
3
Minimum DSP setup time  
External device hold time requirement  
External device setup time requirement  
Control signal route delay  
External device hold time  
4
5
6
7
8
External device access time  
DSP hold time requirement  
DSP setup time requirement  
Data route delay  
9
10  
11  
ECLKOUTx  
(Output from DSP)  
1
ECLKOUTx  
(Input to External Device)  
2
3
Control Signals  
(Output from DSP)  
4
5
6
Control Signals  
(Input to External Device)  
7
8
Data Signals  
(Output from External Device)  
9
10  
11  
Data Signals  
(Input to DSP)  
† Control signals include data for Writes.  
‡ Data signals are generated during Reads from an external device.  
Figure 15. Board-Level Input/Output Timings  
79  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
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