ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
ASYNCHRONOUS MEMORY TIMING
†‡§
timing requirements for asynchronous memory cycles for EMIFA module
(see Figure 22 and Figure 23)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
3
4
6
7
t
t
t
t
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
6.5
1
ns
ns
ns
ns
su(EDV-AREH)
h(AREH-EDV)
Setup time, ARDY valid before ECLKOUTx high
Hold time, ARDY valid after ECLKOUTx high
3
su(ARDY-EKO1H)
h(EKO1H-ARDY)
1
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory
द#
cycles for EMIFA module
(see Figure 22 and Figure 23)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
RS * E − 1.5
RH * E − 1.9
1
MAX
7
1
2
t
t
t
t
t
t
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUTx high to ARE valid
ns
ns
ns
ns
ns
ns
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
5
8
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUTx high to AWE valid
WS * E − 1.7
WH * E − 1.8
1.3
9
10
7.1
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
¶
#
E = ECLKOUT1 period in ns for EMIFA or EMIFB
Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
85
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