ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
INPUT AND OUTPUT CLOCKS (CONTINUED)
ECLKIN
1
6
3
4
4
5
2
ECLKOUT1
Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA
†‡§
and EMIFB modules
(see Figure 21)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
¶
1
2
3
4
5
6
t
t
t
t
t
t
Period jitter, ECLKOUT2
0
175
ps
ns
ns
ns
ns
ns
J(EKO2)
Pulse duration, ECLKOUT2 high
0.5NE − 0.7
0.5NE − 0.7
0.5NE + 0.7
w(EKO2H)
w(EKO2L)
Pulse duration, ECLKOUT2 low
0.5NE + 0.7
Transition time, ECLKOUT2
1
8
8
t(EKO2)
Delay time, ECLKIN high to ECLKOUT2 high
Delay time, ECLKIN high to ECLKOUT2 low
3
3
d(EKIH-EKO2H)
d(EKIH-EKO2L)
†
‡
The reference points for the rise and fall transitions are measured at V
OL
MAX and V MIN.
OH
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
N = the EMIF input clock divider; N = 1, 2, or 4.
§
¶
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
5
6
ECLKIN
1
3
4
4
2
ECLKOUT2
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
84
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