ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
clock PLL (continued)
†‡
Table 31. TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ and ZLZ PACKAGES − 23 x 23 mm BGA
CLKMODE
CLKMODE1 CLKMODE0 (PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
TYPICAL
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
LOCK TIME
§
(µs)
0
0
1
1
0
1
0
1
Bypass (x1)
0−100
42−75
42−75
25−50
0−100
252−450
504−900
500−1000
0−25
0−16.6
42−75
N/A
x6
63−112.5
126−225
125−250
x12
x20
84−150
75
83.3−166.6
†
‡
These clock frequency range values are applicable to a C64x−600, −720, −850, and −1000-MHz speed devices. For more detailed information,
see the CLKIN timing requirements table for the specific device speed.
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock
modes (x6, x12, or x20). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is
x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
§
68
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