欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第68页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第69页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第70页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第71页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第73页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第74页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第75页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第76页  
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ  
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ  
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
Table 32. Characteristics of the Power-Down Modes  
PRWD FIELD  
(BITS 15−10)  
POWER-DOWN  
MODE  
WAKE-UP METHOD  
EFFECT ON CHIP’S OPERATION  
Input clock to the PLL stops generating clocks. All register and  
internal RAM contents are preserved. All functional I/O “freeze” in  
the last state when the PLL clock is turned off. Following reset, the  
PLL needs time to re-lock, just as it does following power-up.  
Wake-up from PD3 takes longer than wake-up from PD2 because  
the PLL needs to be re-locked, just as it does following power-up.  
PD3  
011100  
Wake by a device reset  
All others  
Reserved  
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or  
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,  
peripherals will not operate according to specifications.  
C64x power-down mode with an emulator  
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow  
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed  
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable  
should be removed.  
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution  
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP  
reset will be required to get the DSP out of PD2/PD3.  
power-supply sequencing  
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,  
systems should be designed to ensure that neither supply is powered up for extended periods of time  
(>1 second) if the other supply is below the proper operating voltage.  
In addition, for proper device initialization, device reset (RESET) must be held active (low) during device power  
ramp and should not be released until the PLL becomes stable.  
power-supply design considerations  
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O  
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).  
72  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
 
 复制成功!