ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
clock PLL (continued)
3.3 V
CPU Clock
C1
C2
EMI
/2
Peripheral Bus
filter
10 µF 0.1 µF
/8
/4
/6
Timer Internal Clock
PLLV
CLKOUT4,
McBSP Internal Clock
CLKMODE0
CLKMODE1
CLKOUT6
PLLMULT
PLL
x6, x12, x20
ECLKIN_SEL (DEVCFG.[17,16]
and DEVCFG.[15,14])
00 01 10
CLKIN
PLLCLK
1
0
/4
/2
ECLKIN
EK2RATE
(GBLCTL.[19,18])
EMIF
00 01 10
Internal to C64x
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 31.)
ECLKOUT1 ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
.
DD
Figure 6. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
67
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