欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第67页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第68页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第69页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第70页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第72页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第73页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第74页浏览型号TMS320C6416TZLZ7的Datasheet PDF文件第75页  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ  
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ  
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
31  
16  
15  
14  
13  
12  
11  
PD2  
R/W-0  
10  
9
8
0
Enable or  
Non-Enabled  
Interrupt Wake  
Enabled  
Interrupt Wake  
Reserved  
R/W-0  
PD3  
PD1  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
7
Legend: R/W−x = Read/write reset value  
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other  
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).  
Figure 10. PWRD Field of the CSR Register  
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the  
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account  
for this delay.  
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where  
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed  
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled  
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order  
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect  
upon PD1 mode termination by an enabled interrupt.  
PD2 and PD3 modes can only be aborted by device reset. Table 32 summarizes all the power-down modes.  
Table 32. Characteristics of the Power-Down Modes  
PRWD FIELD  
(BITS 15−10)  
POWER-DOWN  
MODE  
WAKE-UP METHOD  
EFFECT ON CHIP’S OPERATION  
000000  
001001  
No power-down  
PD1  
CPU halted (except for the interrupt logic)  
Wake by an enabled interrupt  
Power-down mode blocks the internal clock inputs at the  
boundary of the CPU, preventing most of the CPU’s logic from  
switching. During PD1, EDMA transactions can proceed  
between peripherals and internal memory.  
Wake by an enabled or  
non-enabled interrupt  
010001  
011010  
PD1  
Output clock from PLL is halted, stopping the internal clock  
structure from switching and resulting in the entire chip being  
halted. All register and internal RAM contents are preserved. All  
functional I/O “freeze” in the last state when the PLL clock is  
turned off.  
PD2  
Wake by a device reset  
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or  
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,  
peripherals will not operate according to specifications.  
71  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443