ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 43. HPI32 Read Timing (HAS Not Used, Tied High)
19
†
HAS
11
11
10
10
HCNTL[1:0]
HR/W
18
3
‡
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 44. HPI32 Read Timing (HAS Used)
112
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