ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
(CONTINUED)
timing requirements for serial EEPROM interface (see Figure 50)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
8
9
t
t
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
50
0
ns
ns
su(DIV-CLKH)
h(CLKH-DIV)
†
switching characteristics over recommended operating conditions for serial EEPROM interface
(see Figure 50)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
TYP
MAX
1
2
t
t
Pulse duration, XSP_CS low
4092P
0
ns
ns
w(CSL)
Delay time, XSP_CLK low to XSP_CS low
d(CLKL-CSL)
3
4
5
6
7
t
t
t
t
t
Delay time, XSP_CS high to XSP_CLK high
Pulse duration, XSP_CLK high
2046P
2046P
2046P
2046P
2046P
ns
ns
ns
ns
ns
d(CSH-CLKH)
w(CLKH)
Pulse duration, XSP_CLK low
w(CLKL)
Output setup time, XSP_DO valid before XSP_CLK high
Output hold time, XSP_DO valid after XSP_CLK high
osu(DOV-CLKH)
oh(CLKH-DOV)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
2
1
XSP_CS
3
4
5
XSP_CLK
7
6
XSP_DO
9
8
XSP_DI
Figure 50. PCI Serial EEPROM Interface Timing
116
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
