ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
(CONTINUED)
timing requirements for PCI inputs (see Figure 49)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
5
6
t
t
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
7
0
ns
ns
su(IV-PCLKH)
h(IV-PCLKH)
switching characteristics over recommended operating conditions for PCI outputs (see Figure 49)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Delay time, PCLK high to output valid
11
ns
ns
ns
ns
d(PCLKH-OV)
d(PCLKH-OIV)
d(PCLKH-OLZ)
d(PCLKH-OHZ)
Delay time, PCLK high to output invalid
2
2
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
28
PCLK
1
2
Valid
PCI Output
PCI Input
3
4
Valid
5
6
Figure 49. PCI Input/Output Timing
115
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