ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
HOST-PORT INTERFACE (HPI) TIMING
†‡
timing requirements for host-port interface cycles (see Figure 39 through Figure 46)
−600
−850
−720
−1G
NO.
UNIT
MIN
MAX
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
5
ns
ns
ns
ns
ns
ns
ns
ns
su(SELV-HSTBL)
h(HSTBL-SELV)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2.4
¶
3
Pulse duration, HSTROBE low
4P
4P
5
4
Pulse duration, HSTROBE high between consecutive accesses
w(HSTBH)
§
Setup time, select signals valid before HAS low
10
11
12
13
su(SELV-HASL)
h(HASL-SELV)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
5
2.8
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
t
2
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
su(HASL-HSTBL)
2.1
h(HSTBL-HASL)
†
‡
§
¶
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
†‡
cycles (see Figure 39 through Figure 46)
−600
−850
−720
−1G
NO.
PARAMETER
UNIT
MIN
1.3
2
MAX
#
6
7
t
t
t
t
t
Delay time, HSTROBE low to HRDY high
4P + 8
ns
ns
ns
ns
ns
d(HSTBL-HRDYH)
d(HSTBL-HDLZ)
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
Delay time, HSTROBE low to HD low impedance for an HPI read
Delay time, HD valid to HRDY low
8
−3
9
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
1.5
15
12
16
t
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P + 8
ns
d(HSTBL-HDV)
†
‡
#
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
109
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