ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
†‡
timing requirements for PCLK (see Figure 47)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
§
1
2
3
4
t
t
t
t
Cycle time, PCLK
30 (or 8P )
ns
ns
c(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
11
11
1
w(PCLKH)
w(PCLKL)
sr(PCLK)
ns
4
V/ns
†
‡
§
For 3.3-V operation, the reference points for the rise and fall transitions are measured at V
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
Select the parameter value of 30 ns or 8P, whichever is greater.
MAX and V MIN.
IHP
ILP
0.4 DV
Peak to Peak for
3.3V signaling
V MIN
DD
1
4
2
PCLK
3
4
Figure 47. PCLK Timing
timing requirements for PCI reset (see Figure 48)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, PRST
1
ms
w(PRST)
Setup time, PCLK active before PRST high
100
µs
su(PCLKA-PRSTH)
PCLK
PRST
1
2
Figure 48. PCI Reset (PRST) Timing
114
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