TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
6.11 Flash Timing
Table 6-43. Flash Endurance
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
0°C to 85°C (ambient)
0°C to 85°C (ambient)
100
1000
NOTP OTP endurance for the array (write cycles)
1
Table 6-44. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER(1)
16-Bit Word
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
µs
Program
Time
16K Sector
8K Sector
4K Sector
16K Sector
8K Sector
4K Sector
500
250
125
10
ms
ms
ms
S
Erase Time
10
S
10
S
IDD3VFLP
VDD3VFL current consumption during the
Erase/Program cycle
Erase
Program
75
mA
mA
mA
35
IDDP
VDD current consumption during Erase/Program
cycle
140
IDDIOP
VDDIO current consumption during Erase/Program
cycle
20
mA
(1) Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.
Table 6-45. Flash/OTP Access Timing
PARAMETER
Paged flash access time
MIN
36
TYP
MAX
UNIT
ns
ta(fp)
ta(fr)
Random flash access time
OTP access time
36
ns
ta(OTP)
60
ns
Equations to compute the Flash page wait-state and random wait-state in Table 6-46 are as follows:
ta(fp)
Flash Page Wait-State
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 0, whichever is larger
tc(SCO)
ta(fr)
(round up to the next highest integer) or 1, whichever is larger
Flash Random Wait-State
+
ǒ Ǔ* 1
ƪ ƫ
tc(SCO)
Equation to compute the OTP wait-state in Table 6-46 is as follows:
ta(OTP)
OTP Wait-State
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 1, whichever is larger
tc(SCO)
124
Electrical Specifications
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