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TMS320F2809 参数 Datasheet PDF下载

TMS320F2809图片预览
型号: TMS320F2809
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 134 页 / 1127 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F2809, TMS320F2808, TMS320F2806  
TMS320F2802, TMS320F2801, UCD9501  
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs  
www.ti.com  
SPRS230HOCTOBER 2003REVISED JUNE 2006  
6.9.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)  
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels  
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or  
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected  
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are  
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register  
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold  
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC  
clocks wide (maximum).  
NOTE  
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,  
and not in other combinations (such as A1/B3, etc.).  
Sample n  
Sample n+2  
Sample n+1  
Analog Input on  
Channel Ax  
Analog Input on  
Channel Bx  
ADC Clock  
Sample and Hold  
SH Pulse  
SMODE Bit  
t
d(SH)  
t
dschA0_n+1  
t
SH  
ADC Event Trigger from  
ePWM or Other Sources  
t
t
dschA0_n  
dschB0_n+1  
t
dschB0_n  
Figure 6-24. Simultaneous Sampling Mode Timing  
Table 6-42. Simultaneous Sampling Mode Timing  
AT 12.5 MHz  
ADC CLOCK,  
tc(ADCCLK) = 80 ns  
SAMPLE n  
SAMPLE n + 1  
REMARKS  
td(SH)  
Delay time from event trigger to  
2.5tc(ADCCLK)  
sampling  
tSH  
Sample/Hold width/Acquisition  
Width  
(1 + Acqps) *  
tc(ADCCLK)  
80 ns with Acqps = 0 Acqps value = 0-15  
ADCTRL1[8:11]  
td(schA0_n)  
td(schB0_n)  
Delay time for first result to  
appear in Result register  
4tc(ADCCLK)  
320 ns  
400 ns  
240 ns  
240 ns  
Delay time for first result to  
appear in Result register  
5tc(ADCCLK)  
td(schA0_n+1) Delay time for successive results  
to appear in Result register  
(3 + Acqps) * tc(ADCCLK)  
(3 + Acqps) * tc(ADCCLK)  
td(schB0_n+1) Delay time for successive results  
to appear in Result register  
122  
Electrical Specifications