TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
6.9.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
ePWM or Other Sources
t
SH
Figure 6-23. Sequential Sampling Mode (Single-Channel) Timing
Table 6-41. Sequential Sampling Mode Timing
AT 12.5 MHz
SAMPLE n
SAMPLE n + 1
ADC CLOCK,
REMARKS
tc(ADCCLK) = 80 ns
td(SH)
Delay time from event trigger to
2.5tc(ADCCLK)
sampling
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
80 ns with Acqps = 0
320 ns
Acqps value = 0-15
ADCTRL1[8:11]
td(schx_n)
td(schx_n+1)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
Delay time for successive results to
appear in Result register
(2 + Acqps) *
tc(ADCCLK)
160 ns
Electrical Specifications
121
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