TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-37. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)
NO.
12
MIN
8tc(LCO)
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
tw(SPCL)S
14
17
18
tw(SPCL)S
tw(SPCH)S
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC)S
21
22
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
tv(SPCH-SIMO)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
35
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)
0.5tc(SPC)S
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
116
Electrical Specifications
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