TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data Must
Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-18. SPI Master Mode External Timing (Clock Phase = 1)
6.9.6 SPI Slave Mode Timing
Table 6-36 lists the slave mode external timing (clock phase = 0) and Table 6-37 (clock phase = 1).
Figure 6-19 and Figure 6-20 show the timing waveforms.
Table 6-36. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
MIN
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLKCycle time, SPICLK
4tc(LCO)
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
15 td(SPCH-SOMI)S
td(SPCL-SOMI)S
16 tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
19 tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20 tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
35
35
0.75tc(SPC)S
0.75tc(SPC)S
35
35
0.5tc(SPC)S
0.5tc(SPC)S
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Electrical Specifications
115
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