TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
VI(A)
±
10 V
R6
20 kΩ
(see Note B)
R1
(see Note A)
17
14
RFBA
R2 (see Note A)
C1
(see Note C)
R5
20 kΩ
–
A2
+
Latch
DACA
DB7
7
DGND
REFB
AGND
R11
5 kΩ
AGND
R3
(see Note A)
R10
20 kΩ
(see Note B)
VI(B)
±
10 V
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for
VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
DAC LATCH CONTENTS
MSB
LSB
†
11111111
10000001
10000000
01111111
00000001
00000000
† 1 LSB = (2–8)VI
ANALOG OUTPUT
–VI (255/256)
–VI (129/256)
–VI (128/256) = – Vi/2
– VI (127/256)
– VI (1/256)
– VI (0/256) = 0
Table 2. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
MSB
LSB
‡
11111111
10000001
10000000
01111111
00000001
00000000
‡ 1 LSB = (2–7)VI
ANALOG OUTPUT
VI (127/128)
VI (1/128)
0V
– VI (1/128)
– VI (127/128)
– VI (128/128)
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
+
AGND
R9
10 kΩ
(see Note B)
–
8
Latch
8
DACB
+
–
6
DACA/
DACB
15
CS
16
WR
5
RFBB
R4 (see Note A)
C2
(see Note C)
Control
Logic
OUTB
+
AGND
–
A1
A3
DB0
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Input
Buffer
8
8
VDD
OUTA
R7
10 kΩ
(see Note B)
R11
5 kΩ
VOA
R8
20 kΩ
A4
VOB
TI [ TEXAS INSTRUMENTS ]
