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TL16C552AFNR 参数 Datasheet PDF下载

TL16C552AFNR图片预览
型号: TL16C552AFNR
PDF下载: 下载PDF文件 查看货源
内容描述: 双异步通信部件 [DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC时钟
文件页数/大小: 38 页 / 473 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TL16C552A, TL16C552AM  
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT  
WITH FIFO  
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999  
transmitter switching characteristics over recommended ranges of operating free-air temperature  
and supply voltage (see Note 11 and Figures 6, 7, and 8)  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
RCLK  
cycles  
t
t
t
t
t
Delay time, interrupt THRE to SOUT at start  
See Figure 6  
8
24  
d5  
d6  
d7  
d8  
pd2  
RCLK  
cycles  
Delay time, SOUT at start to interrupt THRE ↑  
Delay time, IOW (WR THR) to interrupt THRE ↑  
Delay time, SOUT at start to TXRDY ↓  
See Note 12 and Figure 6  
See Note 12 and Figure 6  
8
9
32  
RCLK  
cycles  
16  
C
= 100 pF,  
RCLK  
cycles  
L
8
See Figures 7 and 8  
C
= 100 pF,  
L
Propagation delay time from IOW (WR THR) to interrupt THRE ↓  
140  
ns  
ns  
ns  
See Figure 6  
C
= 100 pF,  
L
t
Propagation delay time from IOR (RD IIR) to interrupt THRE ↓  
Propagation delay time from IOW (WR THR) to TXRDY ↑  
140  
195  
pd4  
pd5  
See Figure 6  
C
= 100 pF,  
L
t
See Figures 7 and 8  
NOTES: 11. These parameters are not production tested.  
12. When the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.  
receiver switching characteristics over recommended ranges of operating free-air temperature  
and supply voltage (see Note 13 and Figures 9 through 13)  
PARAMETER  
Delay time from stop to INT ↑  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
RCLK  
cycle  
t
d9  
See Note 14  
1
t
t
t
Propagation delay time from RCLK to sample CLK ↑  
100  
150  
150  
ns  
ns  
ns  
pd6  
pd7  
pd8  
Propagation delay time from IOR (RD RBR/RD LSR) to reset interrupt ↓  
Propagation delay time from IOR (RD RBR) to RXRDY ↑  
C = 100 pF  
L
NOTES: 13. These parameters are not production tested.  
14. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are  
delayed three RCLK cycles in FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are  
delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after RDRBR goes active.  
There are eight RCLK cycle delays for trigger change level interrupts.  
modem control switching characteristics over recommended ranges of operating free-air  
temperature and supply voltage, C = 100 pF (see Note 15 and Figure 14)  
L
PARAMETER  
MIN  
MAX  
100  
170  
140  
170  
UNIT  
ns  
t
t
t
t
Propagation delay time from IOW (WR MCR) to RTS (DTR) ↑  
Propagation delay time from modem input (CTS, DSR) to interrupt ↑  
Propagation delay time from IOR (RD MSR) to interrupt ↓  
Propagation delay time from RI to interrupt ↑  
pd9  
ns  
pd10  
pd11  
pd12  
ns  
ns  
NOTE 15: These parameters are not production tested.  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265