TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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Table 2. Voltage Translation
VCCI (SDA AND SCL OF I2C MASTER)
VCCP (P PORT)
(V)
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
(V)
1.8
2.5
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
5
5
5
LOGIC DIAGRAM (POSITIVE LOGIC)
Interrupt
Logic
32
26
INT
LP Filter
ADDR
29
30
SCL
SDA
I2C Bus
Shift
P27–P20
P17–P10
P07–P00
Input
Filter
24 Bits
I/O Port
Register
Control
31
27
28
Write Pulse
Read Pulse
VCCI
VCCP
Power-On
Reset
RESET
25
GND
A. All I/Os are set to inputs at reset.
B. Pin numbers shown are for the RGJ package.
4
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