3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
O
I
O
I
IK
I
OK
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high
Current into any output in the low state
Current into any output in the high state
(3)
Input clamp current
Output clamp current
state
(2)
SN54LVTH16373
SN74LVTH16373
SN54LVTH16373
SN74LVTH16373
V
I
< 0
V
O
< 0
DGG package
θ
JA
Package thermal impedance
(4)
DL package
GQL/ZQL package
GRD/ZRD package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
–65
–0.5
–0.5
–0.5
–0.5
MAX
4.6
7
7
V
CC
+ 0.5
96
128
48
64
–50
–50
70
63
42
36
150
°C
°C
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and V
O
> V
CC
.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
(1)
SN54LVTH16373
MIN
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v
∆t/∆V
CC
T
A
(1)
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
Outpts enabled
200
–55
125
2.7
2
0.8
5.5
–24
48
10
200
–40
85
MAX
3.6
SN74LVTH16373
MIN
2.7
2
0.8
5.5
–32
64
10
MAX
3.6
UNIT
V
V
V
V
mA
mA
ns/V
µs/V
°C
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4