SN74LVC1G58
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SCES415N –NOVEMBER 2002–REVISED DECEMBER 2013
Logic Configurations
V
CC
V
CC
A
A
B
Y
Y
Y
B
A
A
1
2
3
6
5
4
B
Y
1
2
3
6
5
4
B
Y
A
A
B
Y
B
Figure 1. 2-Input NAND Gate
Figure 2. 2-Input AND Gate With Inverted A Input
V
CC
V
CC
A
A
B
Y
Y
B
1
2
3
6
5
4
B
Y
1
2
3
6
5
4
B
Y
A
B
A
B
Y
A
Y
A
Figure 3. 2-Input AND Gate With Inverted B Input
Figure 4. 2-Input OR Gate
V
CC
A
Y
B
A
1
2
3
6
5
4
B
Y
Figure 5. 2-Input XOR Gate
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