SCES415N – NOVEMBER 2002 – REVISED DECEMBER 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
INPUTS
In2
L
L
L
L
H
H
H
H
In1
L
L
H
H
L
L
H
H
In0
L
H
L
H
L
H
L
H
OUTPUT
Y
L
H
L
H
H
H
L
L
Logic Diagram (Positive Logic)
In0
3
4
In1
1
Y
In2
6
Function Selection Table
LOGIC FUNCTION
2-input AND with inverted input
2-input NAND
2-input NAND with both inputs inverted
2-input OR
2-input OR with both inputs inverted
2-input NOR with inverted input
2-input XOR
FIGURE NO.
2
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