SN65HVD72
SN65HVD75
SN65HVD78
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SLLSE11B –MARCH 2012–REVISED JUNE 2012
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
Noise Immunity
The input sensitivity of a standard RS-485 transceiver is ± 200 mV. When the differential input voltage, VID, is
greater than + 200 mV, the receiver output turns high, for VID < –200 mV the receiver outputs low.
R
V
HYS-min
50mV
V
ID
- mV
-70
-20
0
70
V
= 140mVpp
noise-max
Figure 20. SN65HVD7x Noise Immunity
The SN65HVD7x transceiver family implements high receiver noise-immunity by providing a maximum positive-
going input threshold of - 20 mV and a minimum hysteresis of 50 mV. In the case of a noisy input condition
therefore, a differential noise voltage of up to 140 mVPP can be present without causing the receiver output to
change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias
resistors and allows for long haul data transmissions in noisy environments.
Transient Protection
The bus terminals of the SN65HVD7x transceiver family possess on-chip ESD protection against ±15 kV human
body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the
HBM-ESD test. The 50 % higher charge capacitance, CS, and 78 % lower discharge resistance, RD of the IEC-
model produce significantly higher discharge currents than the HBM-model.
R
R
D
C
40
35
30
25
20
15
10
5
50M
(1M)
330Ω
(1.5k)
10kV IEC
High-Voltage
Pulse
Generator
Device
Under
Test
150pF
C
S
(100pF)
10kV HBM
0
0
50
100
150
200
250
300
Time - ns
Figure 21. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The implementation of IEC-ESD protection on-chip increases the robustness of equipment significantly, which
most likely experience discharge events due to human contact with connectors and cables. Designers may also
want to implement protection against much longer duration transients, typically referred to as surge transients.
Figure 9 therefore suggests two circuit designs providing protection against light and heavy surge transients, in
addition to ESD and EFT transients. Table A1 presents the associated bill of material.
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