欢迎访问ic37.com |
会员登录 免费注册
发布采购

SN65HVD75 参数 Datasheet PDF下载

SN65HVD75图片预览
型号: SN65HVD75
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V电源RS - 485与IEC ESD保护 [3.3V-Supply RS-485 with IEC ESD Protection]
分类和应用:
文件页数/大小: 25 页 / 778 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号SN65HVD75的Datasheet PDF文件第9页浏览型号SN65HVD75的Datasheet PDF文件第10页浏览型号SN65HVD75的Datasheet PDF文件第11页浏览型号SN65HVD75的Datasheet PDF文件第12页浏览型号SN65HVD75的Datasheet PDF文件第14页浏览型号SN65HVD75的Datasheet PDF文件第15页浏览型号SN65HVD75的Datasheet PDF文件第16页浏览型号SN65HVD75的Datasheet PDF文件第17页  
SN65HVD72  
SN65HVD75  
SN65HVD78  
www.ti.com  
SLLSE11B MARCH 2012REVISED JUNE 2012  
Receiver Failsafe  
The differential receiver is “failsafe” to invalid bus states caused by:  
open bus conditions such as a disconnected connector  
shorted bus conditions such as cable damage shorting the twisted-pair together, or  
idle bus conditions that occur when no driver on the bus is actively driving  
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the  
receiver is not indeterminate.  
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range  
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver  
output must output a High when the differential input VID is more positive than +200 mV, and must output a Low  
when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance  
are VIT+ and VIT-and VHYS. As seen in the Electrical Characteristics table, differential signals more negative than -  
200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will  
always cause a High receiver output.  
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output  
will be High. Only when the differential input is more negative than VIT-will the receiver output transition to a Low  
state. So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis  
value VHYS (the separation between VIT+ and VIT-) as well as the value of VIT+  
.
Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring  
no spurious bits.  
Low-Power Standby Mode  
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the  
enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode.  
This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs  
are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode.  
In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less  
than 100 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.  
Copyright © 2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s): SN65HVD72 SN65HVD75 SN65HVD78  
 
 复制成功!