RM48L950
RM48L750
RM48L550
SPNS174–SEPTEMBER 2011
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 5-13. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
Figure 5-14. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
146
Peripheral Information and Electrical Specifications
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