RM48L950
RM48L750
RM48L550
SPNS174–SEPTEMBER 2011
www.ti.com
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 5-9. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 5-10. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
142
Peripheral Information and Electrical Specifications
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