SPNS174
–
SEPTEMBER 2011
5.9.5
SPI Slave Mode I/O Timings
Table 5-21. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)
(1) (2) (3) (4)
NO.
1
2
(6)
3
(6)
4
(6)
Parameter
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
d(SPCH-SOMI)S
t
d(SPCL-SOMI)S
Cycle time, SPICLK
(5)
MIN
40
14
14
14
14
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
Setup time, SPISIMO before SPICLK low (clock polarity =
0)
Setup time, SPISIMO before SPICLK high (clock polarity =
1)
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
Hold time, SPISIMO data valid after S PICLK high (clock
polarity = 1)
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
2
2
2
2
2
2
1.5t
c(VCLK)
1.5t
c(VCLK)
t
f(ENAn)
MAX
256t
c(VCLK)
Unit
ns
ns
ns
t
rf(SOMI)
+ 18
t
rf(SOMI)
+ 18
ns
5
(6)
t
h(SPCH-SOMI)S
t
h(SPCL-SOMI)S
ns
6
(6)
t
su(SIMO-SPCL)S
t
su(SIMO-SPCH)S
ns
7
(6)
t
h(SPCL-SIMO)S
t
h(SPCH-SIMO)S
ns
8
t
d(SPCL-SENAH)S
t
d(SPCH-SENAH)S
2.5t
c(VCLK)
+t
r(ENAn)
2.5t
c(VCLK)
+
tr(ENAn)
t
c(VCLK)
+t
f(ENAn)
+1
4
ns
9
(1)
(2)
(3)
(4)
(5)
(6)
t
d(SCSL-SENAL)S
ns
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
If the SPI is in slave mode, the following must be true: t
c(SPC)S
≥
(PS + 1) t
c(VCLK)
, where PS = prescale value set in SPIFMTx.[15:8].
For rise and fall timings, see the
"switching
characteristics for output timings versus load capacitance" table.
t
c(VCLK)
= interface clock cycle time = 1 /f
(VCLK)
When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)S
≥
(PS +1)t
c(VCLK)
≥
40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)S
= 2t
c(VCLK)
≥
40ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright
©
2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
focus.ti.com:
145
PRODUCT PREVIEW
TI [ TEXAS INSTRUMENTS ]
