RM48L950
RM48L750
RM48L550
www.ti.com
SPNS174–SEPTEMBER 2011
Table 5-20. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
ns
(4)
1
tc(SPC)M
Cycle time, SPICLK
40
256tc(VCLK)
0.5tc(SPC)M + 3
2(5) tw(SPCH)M
tw(SPCL)M
3(5) tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
ns
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 5
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
4(5) tv(SIMO-SPCH)M
Valid time, SPICLK high after
SPISIMO data valid (clock polarity =
0)
tv(SIMO-SPCL)M
Valid time, SPICLK low after
0.5tc(SPC)M – 5
SPISIMO data valid (clock polarity =
1)
5(5) tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
6(5) tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
7(5) tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr(SPC) – 3
ns
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf(SPC) – 3
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tr(SPC)
tf(SPC)
5
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
5
8(6) tC2TDELAY
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
(C2TDELAY+2) * tc(VCLK)
-
-
-
-
-
-
-
-
tf(SPICS) + tr(SPC) – 15
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) – 15
Setup time CS
active until SPICLK
low (clock polarity =
1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M
+
ns
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) – 15
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
-
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) – 15
-
9(6) tT2CDELAY
Hold time SPICLK low CS until
inactive (clock polarity = 0)
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
4
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
8
+
ns
ns
+
+
Hold time SPICLK high until CS
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
4
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
8
+
10 tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)* tc(VCLK)
-
(C2TDELAY+1)*tc(VCLK)
ns
ns
tf(SPICS) – 25
11 tSPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
focus.ti.com: RM48L950 RM48L750 RM48L550
143
TI [ TEXAS INSTRUMENTS ]
