RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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When POM is used to overlay the flash on to internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
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The POM implements a timeout feature to detect this exact scenario. The timeout needs to be
enabled whenever POM overlay is enabled.
The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
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The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If
so, then the application can assume that the timeout is caused by a bus contention between the
POM transaction and another master accessing the same memory region. The abort handlers need
to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to
a timeout from the POM.
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System Information and Electrical Specifications
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