RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
L SIZE
START
END
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
MIBADC1 RAM
8kB
Look-Up Table for ADC1 wrapper.
Starts at address offset 0x2000 and
ends at address offset 0x217F. Wrap
around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
PCS[31]
0xFF3E_0000
0xFF3F_FFFF
128kB
MibADC1 Look-
Up Table
384B
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET2 RAM
N2HET1 RAM
PCS[34]
PCS[35]
0xFF44_0000
0xFF46_0000
0xFF45_FFFF
128kB
128kB
16kB
16kB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
0xFF47_FFFF
0xFF4D_FFFF
N2HET2 TU2
RAM
PCS[38]
PCS[39]
0xFF4C_0000
0xFF4E_0000
128kB
128kB
1kB
1kB
Abort
Abort
N2HET1 TU1
RAM
0xFF4F_FFFF
Debug Components
0xFFA0_0FFF
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
0xFFA0_0000
4kB
4kB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
CSCS1
CSCS4
0xFFA0_1000
0xFFA0_4000
0xFFA0_1FFF
0xFFA0_4FFF
4kB
4kB
4kB
4kB
POM
Abort
Peripheral Control Registers
Reads return zeros, writes have no
effect
HTU1
HTU2
PS[22]
PS[22]
PS[17]
PS[17]
PS[16]
PS[15]
PS[15]
PS[10]
PS[8]
0xFFF7_A400 256B
0xFFF7_A4FF
0xFFF7_A5FF
0xFFF7_B8FF
0xFFF7_B9FF
0xFFF7_BDFF
0xFFF7_C1FF
0xFFF7_C3FF
0xFFF7_D4FF
0xFFF7_DDFF
0xFFF7_DFFF
0xFFF7_E1FF
0xFFF7_E4FF
0xFFF7_E5FF
256B
256B
256B
256B
256B
512B
512B
256B
512B
512B
512B
256B
256B
Reads return zeros, writes have no
effect
0xFFF7_A500
0xFFF7_B800
0xFFF7_B900
0xFFF7_BC00
0xFFF7_C000
0xFFF7_C200
0xFFF7_D400
0xFFF7_DC00
0xFFF7_DE00
0xFFF7_E000
0xFFF7_E400
0xFFF7_E500
256B
256B
256B
512B
512B
512B
256B
512B
512B
512B
256B
256B
Reads return zeros, writes have no
effect
N2HET1
N2HET2
GIO
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
MIBADC1
MIBADC2
I2C
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
DCAN1
DCAN2
DCAN3
LIN
Reads return zeros, writes have no
effect
PS[8]
Reads return zeros, writes have no
effect
PS[7]
Reads return zeros, writes have no
effect
PS[6]
Reads return zeros, writes have no
effect
SCI
PS[6]
Copyright © 2012, Texas Instruments Incorporated
System Information and Electrical Specifications
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