PGA400-Q1
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SLDS186 –MARCH 2012
6.25.8 Main Oscillator Watchdog
There is watch dog monitor for the main oscillator clock whether using the internal 40MHz oscillator or the
external crystal input. When the frequency is outside the range of 35-45MHz the entire device is reset.
The main oscillator watchdog can be disabled using MAIN_OSC_WD_EN bit in the ENABLE CONTROL
register.
6.25.9 Software Watchdog
The device also implements a software watchdog. This watchdog has to be serviced by software every
500ms. If the software does not service the watchdog within 500ms of the last service, then the 8051W
core is reset. The software services the watchdog by toggling the state of an internal pin between the two
blocks. The state of this pin cannot be read back to the 8051W. If this function is not desired the software
watchdog can be disabled using CPU_WD_EN bit in the ENABLE CONTROL register.
When the software watchdog times out and resets the 8051W, DAC1 and DAC2 registers are reset to 0,
which causes VOUT1 and VOUT2 to be driven to 0V. The remaining ESFRs retains the settings from prior
to the reset events. This implies that CPU_WD_EN also remains set.
6.26 Low Power Mode
The device has multiple low power modes. In each mode, certain functional blocks can be turned on or off
through the use of different ESFRs. Table 6-6 lists which bits in each ESFR that disables certain blocks of
the device.
Table 6-6. Low Power Control
CONTROL BIT
ESFR
CONTROL ACTION
Enables/Disables VBRG supply
Enables/Disables DAC2
VBRG_EN
DAC2_EN
AFE_EN
SENCTRL
DECCTRL
DECCTRL
EN_CTRL2
EN_CTRL2
Enables/Disable AFE
EN_DI_IF_CLK
Enable/Disable Digital Interface
Enable/Disable EEPROM clock
EN_EEPROM_CTRL_CLK
The following blocks does not enter low power mode at any time:
•
•
Microprocessor – the microprocessor continues to operate at the same frequency
OTP/EEPROM – The memory is kept alive and runs at the same speed VOUT1/OWI
Copyright © 2012, Texas Instruments Incorporated
FUNCTIONAL DESCRIPTIONS
39
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