ADS1259
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SBAS424C –JUNE 2009–REVISED MARCH 2010
BASIC CONNECTION
The ADS1259 basic connections are shown in Figure 63. The diagram shows the ADS1259 operating with an
internal oscillator and with internal reference. Dual ±2.5V analog power supplies are also shown. Pins 6-9 are the
SPI port connection. The remaining digital I/O pins connect to the controller I/O. Note that the minimum
configuration of the digital I/O may include only SCLK, DIN, and DOUT.
+2.5V
(1)
20W to 50W
ADS1259
1
2
20
19
18
17
16
15
14
13
12
11
1mF
(+)
AINP
AINN
AVDD
AVSS
-2.5V
Signal Input
10nF(2)
(-)
1mF
-
3
20W to 50W
VREFN
RESET/PWDN
START
SYNCOUT
CS
2.5V
Reference Output
1mF
Controller I/O
1mF
4
+
+
VREFP
4.7kW
+
5
Drives the PGA280
SYNCIN Pin
REFOUT
DVDD
6
1MW
+3.3V
1mF
7
SCLK
DGND
1mF
Controller SPI Port
8
+
DIN
BYPASS
XTAL2
9
DOUT
10
Controller I/O
XTAL1/CLKIN
DRDY
1MW
(1) It is recommended to buffer the ADS1259 inputs. The output isolation resistors may be incorporated within the amplifier feedback loop.
(2) Low distortion C0G or film capacitor recommended.
Figure 63. ADS1259 Basic Connection Diagram
LAYOUT
Place the input buffer and input decoupling capacitors close to the ADS1259 inputs. The bypass capacitors for
power-supply and reference decoupling should also be placed close to the device. In some cases, it may be
necessary to use a split ground plane in which digital return currents of external components are routed away
from the ADS1259. In this case, connect the grounds at the power supply.
CONFIGURATION GUIDE
Configuration of the ADS1259 involves configuring the device hardware (power supply, I/O pins, etc) and device
register settings. The registers are configured by commands sent via the device SPI port.
Power Supplies
The ADS1259 analog section operates either with a single +5V or dual ±2.5V supplies. The digital section
operates from +2.7V to +5V. The digital and analog power supplies may be tied together (+5V only).
Reference
Select either the internal reference or an external reference for the ADS1259 (see the Reference section). The
default is external reference. Figure 63 depicts the internal reference connection.
Clock
Choose the desired clock source (see the Clock Source section). Figure 63 depicts the internal clock operation.
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