ADS1259
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SBAS424C –JUNE 2009–REVISED MARCH 2010
REGISTER MAP
The operation of the ADS1259 is controlled through a set of registers. Collectively, the registers contain all the
information needed to configure the part, such as data rate, calibration, etc. Table 20 shows the register map.
Table 20. Register Map
RESET
ADDRESS
REGISTER
CONFIG0
CONFIG1
CONFIG2
OFC0
VALUE
BIT 7
1
BIT 6
0
BIT 5
ID1
BIT 4
ID0
BIT 3
0
BIT 2
RBIAS
DELAY2
DR2
BIT 1
0
BIT 0
SPI
0h
1h
2h
3h
4h
5h
6h
7h
8h
10XX0101b
00001000b
XX000000b
00000000b
00000000b
00000000b
00000000b
00000000b
01000000b
FLAG
DRDY
OFC07
OFC15
OFC23
FSC07
FSC15
FSC23
CHKSUM
EXTCLK
OFC06
OFC14
OFC22
FSC06
FSC14
FSC22
0
SINC2
PULSE
OFC04
OFC12
OFC20
FSC04
FSC12
FSC20
EXTREF
0
DELAY1
DR1
DELAY0
DR0
SYNCOUT
OFC05
OFC13
OFC21
FSC05
FSC13
FSC21
OFC03
OFC11
OFC19
FSC03
FSC11
FSC19
OFC02
OFC10
OFC18
FSC02
FSC10
FSC18
OFC01
OFC09
OFC17
FSC01
FSC09
FSC17
OFC00
OFC08
OFC16
FSC00
FSC08
FSC16
OFC1
OFC2
FSC0
FSC1
FSC2
CONFIG0: CONFIGURATION REGISTER 0 (Address = 0h)
7
1
6
0
5
4
3
2
1
0
0
ID1
ID0
0
RBIAS
SPI
Reset value = 10XX0101b.
Bit 7
Reserved (read-only)
Always returns '1'.
Bit 6
Reserved (read-only)
Always returns '0'.
Bits 5-4
Bit 3
ID[1:0]: Factory-programmed identification bits (read-only)
(Note that these bits may change without notification.)
Reserved
Always write '0'.
Bit 2
RBIAS: Internal reference bias
0 = Internal reference bias disabled
1 = Internal reference bias enabled (default)
Bit 1
Bit 0
Reserved
Always write '0'.
SPI: SCLK timeout of SPI interface
0 = SPI timeout disabled
1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles
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