ADS1259
www.ti.com
SBAS424C –JUNE 2009–REVISED MARCH 2010
CONFIG2: CONFIGURATION REGISTER 2 (Address = 2h)
7
6
5
4
3
2
1
0
DRDY
EXTCLK
SYNCOUT
PULSE
0
DR2
DR1
DR0
Reset value = XX000000b.
Bit 7
Bit 6
DRDY: Data ready (read-only)
This bit duplicates the state of the DRDY pin. Poll this bit to indicate that data are ready. When
DRDY is low, data are ready.
EXTCLK: Clock source (read-only)
0 = Device clock source is internal oscillator
1 = Device clock source is external clock
Note that the ADS1259 selects the clock source automatically.
Bit 5
Bit 4
SYNCOUT: SYNCOUT clock enable
0 = SYNCOUT disabled (default)
1 = SYNCOUT enabled
Note that if disabled, the output is driven low.
PULSE: Conversion Control mode select
0 = Gate Control mode (default)
1 = Pulse Control mode
Bit 3
Reserved
Always write '0'
Bits 2-0
DR[2:0] Data rate setting
000 = 10SPS (default)
001 = 16.6SPS
010 = 50SPS
011 = 60SPS
100 = 400SPS
101 = 1200SPS
110 = 3600SPS
111 = 14400SPS
NOTE: fCLK = 7.3728MHz
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Link(s): ADS1259
TI [ TEXAS INSTRUMENTS ]
