PCM9211
SBAS495 –JUNE 2010
www.ti.com
Register 2Ah, INT0 Output Cause Mask Setting
(Address: 2Ah, Write and Read)
DATA
B7
B6
MNPCM0
1
B5
MEMPHF0
1
B4
MDTSCD0
1
B3
MCSRNW0
1
B2
MPCRNW0
1
B1
MFSCHG0
1
B0
RSV
1
Reg Name
Default Value
Memo
MERROR0
1
MERROR0: ERROR Port Output Status
0: Not masked
1: Masked (default)
MNPCM0: NPCM Port Output Status
0: Not masked
1: Masked (default)
This register setting follows the register setting of non-PCM data identification.
MEMPHF0: Emphasis Flag in Channel Status
0: Not masked
1: Masked (default)
MDTSCD0: DTS-CD/LD Sync Detection
0: Not masked
1: Masked (default)
This detection condition depends on the register setting for DTS-CD/LD detection conditions.
MCSRNW0: Channel Status Data of Beginning 48-bit Renewal
0: Not masked
1: Masked (default)
MPCRNW0: Burst Preamble PC Renewal
0: Not masked
1: Masked (default)
MFSCHG0: Renewal Flag of fS Calculator Result
0: Not masked
1: Masked (default)
72
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): PCM9211