PCM9211
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SBAS495 –JUNE 2010
Register 23h, DIR Initial Settings 3/3
(Address: 23h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
XTIWT1
0
B4
XTIWT0
0
B3
PRTPRO1
0
B2
PRTPRO0
1
B1
ERRWT1
0
B0
ERRWT0
0
XTIWT[1:0]: Crystal OSC, Oscillation Start-up Wait Time Setting
00: 25 ms
01: 50 ms
10: 100 ms
11: 200 ms
XTIWT is counted by the PLL generated clock.
These are the resulting values when the PLL is running with a free-run clock because of no S/PDIF input.
After these delay times, the Main Port source changes from DIR to ADC when DIR is unlocked.
PRTPRO[1:0]: Process for Parity Error Detection
00: No process
01: For PCM data only, an 8x continuous parity error is replaced by previous data and muted after ninth
parity error at EPARITY = 1 (default)
10: For PCM and non-PCM data, an 8x continuous parity error is replaced by previous data and muted
after ninth parity error at EPARITY = 1
11: Reserved (The definition of Non-PCM depends on the Non-PCM Definition Setting Register)
Validity flag, user bit, channel status, Non-PCM and DTS-CD detection should be refreshed by waiting
more than 192/fS without any parity error.
ERRWT[1:0]: ERROR Release Wait Time Setting
00: ERROR Release after 48 counts of preamble B (Default), 192 ms at fS = 48 kHz
01: ERROR Release after 12 counts of preamble B
10: ERROR Release after six counts of preamble B
11: ERROR Release after three counts of preamble B
These counts are only available when DIR is unlocked or DIR sampling frequency is changed or exceeds
limits defined by DIR Acceptable fS Range Setting and Mask registers.
CLKST also uses ERRWT to release.
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