PCM9211
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SBAS495 –JUNE 2010
OUTPUT REGISTER CONSTRUCTION
The output 8-bit register is subdivided into three sections. The first four bits show the decoded result. The next
three bits signify the source; the final bit signifies the calculator status (finished or not).
The lock range of the counter (to the specified fS given in Table 9) are any clock rate within ±2%. The relation
between the nominal fS and actual measured fS range is shown in Table 9.
Table 9. Calculated Port Sampling Frequency Output
CALCULATED SAMPLING FREQUENCY OUTPUT
ACTUAL SAMPLING
NOMINAL fS
Out of range
8 kHz
FREQUENCY RANGE (MIN)
Out of range
PFSOUT3
PFSOUT2
PFSOUT1
PFSOUT0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7.84 kHz to 8.16 kHz
11.025 kHz
12 kHz
10.8045 kHz to 11.2455 kHz
11.76 kHz to 12.24 kHz
15.68 kHz to 16.32 kHz
21.609 kHz to 22.491 kHz
23.52 kHz to 24.48 kHz
31.36 kHz to 32.64 kHz
43.218 kHz to 44.982 kHz
47.04 kHz to 48.96 kHz
62.72 kHz to 65.28 kHz
86.436 kHz to 89.964 kHz
94.08 kHz to 97.92 kHz
125.44 kHz to 130.56 kHz
172.872 kHz to 179.928 kHz
188.16 kHz to 195.84 kHz
16 kHz
22.05 kHz
24 kHz
32 kHz
44.1 kHz
48 kHz
64 kHz
88.2 kHz
96 kHz
128 kHz
176.4 kHz
192 kHz
Copyright © 2010, Texas Instruments Incorporated
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