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SLES081A − JUNE 2003 – REVISED MAY 2004
Functionality of ST and ADDR Bit Combinations
ST
0
ADDR
FUNCTION
0
1
0
1
HID status write
0
HID status write and descriptor ROM address read
Descriptor ROM data write
Reserved
1
1
USB HOST INTERFACE SEQUENCE
Power-On, Attach, and Playback Sequence
The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a
connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for
the audio data (idle state), the analog output is set to bipolar zero (BPZ).
When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio data,
into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent
start-of-frame (SOF) packet.
3.3 V
(Typ.)
V
DD
2.0 V (Typ.)
0 V
st
1
nd
2 Audio Data
Bus Reset
Set Configuration
Audio Data
Bus Idle
D+/D−
SOF
SOF
SOF
SSPND
BPZ
V
L
R
OUT
V
OUT
Device Setup
1 ms
700 µs
Internal Reset
Ready for Setup
Ready for Playback
Figure 28. Initial Sequence
25
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