6.6 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (see Note 5 and Figure 6–1 and Figure 6–4)
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
PCLK to shared signal
valid delay time
t
11
val
inv
t
Propagation delay time
Enable time,
C
= 50 pF, See Note 6
L
ns
pd
PCLK to shared signal
invalid delay time
t
2
2
t
t
t
ns
ns
en
on
off
high-impedance-to-active delay time from PCLK
Disable time,
t
28
dis
active-to-high-impedance delay time from PCLK
t
t
Setup time before PCLK valid
Hold time after PCLK high
t
, See Note 4
7
0
ns
ns
su
su
t , See Note 4
h
h
5. This data sheet uses the following conventions to describe time (t) intervals. The format is: t , where subscript A indicates the type
A
ofdynamicparameterbeingrepresented. Oneofthefollowingisused:t =propagationdelaytime, t = delay time, t = setup time,
pd su
d
and t = hold time.
h
6. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
6–5
TI [ TEXAS INSTRUMENTS ]
