Table 2–8. Secondary PCI System
TERMINAL
PCM
I/O
DESCRIPTION
PGF
NAME
NUMBER NUMBER
61
59
57
55
53
67
65
63
61
59
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus.
Each secondary bus device samples all secondary PCI signals at the rising edge of its
corresponding S_CLKOUT input.
O
Secondary PCI bus clock input. This input syncronizes the PCI2250 to the secondary bus
clocks.
51
57
I
I
S_CLK
Secondary external arbiter enable. When this signal is high, the secondary external arbiter
is enabled. When the external arbiter is enabled, the S_REQ0 pin is reconfigured as a
secondary bus grant input to the bridge and S_GNT0 is reconfigured as a secondary bus
master request to the external arbiter on the secondary bus.
S_CFN
49
55
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus
reset bit of the bridge control register (offset 3Eh, see Section 4.32). S_RST is asynchronous
with respect to the state of the secondary interface CLK signal.
S_RST
48
54
O
2–9
TI [ TEXAS INSTRUMENTS ]
