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ZHCSFG0 –SEPTEMBER 2016
7.6.6 Adjustment Registers
7.6.6.1 Adjustment Registers 44-50
Figure 46. Adjustment Registers 44-50
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Adjustment Registers 44-50 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
7.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
Figure 47. Adjustment Register 51
7
SEL_RES_2
R
6
SEL_RES_1
R
5
SEL_RES_0
R
4
3
2
Reserved
R
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Adjustment Register 51 Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
SEL_RES_2
SEL_RES_1
0
1
CDR Loop Filter Resistor
000: 75,
001: 150
6
010: 225
011: 300
100: 375
101: 450
5
SEL_RES_0
R/W
0
110: 525
111: 600
Default = 225
4:0
Reserved
R/W
0
Reserved
7.6.6.3 Adjustment Registers 52-55
Figure 48. Adjustment Registers 52-55
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Adjustment Registers 52-55 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
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