ONET1131EC
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ZHCSFG0 –SEPTEMBER 2016
7.6.5 Read Only Registers
7.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
Figure 42. Core Level Register 40
7
ADC9
R
6
ADC8
R
5
ADC5
R
4
ADC4
R
3
ADC3
R
2
ADC2
R
1
ADC1
R
0
ADC0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Core Level Register 40 Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Digital representation of the ADC input source (read only)
ADC9 (MSB)
ADC8
0
0
0
0
0
0
0
0
6
R
5
ADC7
R
4
ADC6
R
3
ADC5
R
2
ADC4
R
1
ADC3
R
0
ADC2
R
7.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
Figure 43. Core Level Register 41
7
6
5
4
3
2
1
ADC1
R
0
ADC0
R
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Core Level Register 41 Field Descriptions
Bit
7:2
1
Field
Type
R
Reset
0h
Description
Resereved
ADC1
Reserved
R
0h
Digital representation of the ADC input source (read only)
0
ADC0 (LSB)
R
0h
7.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
Figure 44. RX Registers 42
7
6
5
4
3
2
1
0
Reserved
R
RCLR
R
RCLR
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
Table 21. RX Registers 42 Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
6
RCLR
R
5
4
RCLR
R
3:0
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