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ZHCSFG0 –SEPTEMBER 2016
7.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
Figure 40. TX Register 19
7
6
5
4
3
2
1
0
TXFD_MOD1
R/W
TXFD_MOD0
R/W
TXFD_EN
R/W
TXFD_DIS
R/W
0TXFL_DIS
R/W
TXDIV2
R/W
TXDIV1
R/W
TXDIV0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. TX Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXFD_MOD1
R/W
0
TX frequency detection mode selection
00 = auto selection enabled
01 = Pre-selected to 10.3 Gbps
10 = Pre-select to 11.1 Gbps
11 = test mode (do not use)
6
TXFD_MOD0
R/W
0
TX frequency detector enable bit
5
4
3
TXFD_EN
TXFD_DIS
TXFL_DIS
R/W
R/W
R/W
0
0
0
1 =TX frequency detector is always enabled
0 = TX frequency detector in automatic mode
TX frequency detector disable bit
1 = TX frequency detector is always disabled
0 = TX frequency detector is in automatic mode
TX CDR fast lock disable bit
1 = TX CDR fast lock disabled
0 = TX CDR in fast lock mode
2
1
TXDIV2
TXDIV1
R/W
R/W
0
0
TX Divider Ratio
000: Full-Rate,
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
101: Divide by 32
0
TXDIV0
R/W
0
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