ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
7.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
Figure 45. Core Level Register 43
7
TXCDRLock
R
6
TXCDRLock
R
5
TX_FLT
R
4
TX_DRVDIS
R
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
Table 22. TX Registers 43 Field Descriptions
Bit
Field
Type
Reset
Description
TX CDR lock status bit
1 = TX CDR is not locked
0 = TX CDR is locked
7
TXCDRLock
R
0
Latched low status of bit 7. Cleared when read.
6
5
TXCDRLock (latched Low)
TX_FLT
RCLR
R
0
0
Latched low bit set to 0 when raw status goes low and keep it low even if
raw status goes high.
TX fault status bit
1 = TX fault detected
0 = TX fault not detected
TX driver disable status bit
4
TX_DRVDIS
Reserved
R
R
0
0
1 = TX fault logic disables the driver
0 = TX fault logic does not disable the driver
3:0
Reserved
34
Copyright © 2016, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
