OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-47. McASP2 Switching Characteristics(1)
NO.
PARAMETER
MIN
13
MAX
UNIT
Cycle time, AHCLKX2 internal, AHCLKR2 output
Cycle time, AHCLKR2 external, AHCLKR2 output
Cycle time, AHCLKX2 internal, AHCLKX2 output
Cycle time, AHCLKX2 external, AHCLKX2 output
13
9
tc(AHCLKRX)
ns
13
13
Pulse duration, AHCLKR2 internal, AHCLKR2
output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
Pulse duration, AHCLKR2 external, AHCLKR2
output
10
tw(AHCLKRX)
ns
Pulse duration, AHCLKX2 internal, AHCLKX2
output
Pulse duration, AHCLKX2 external, AHCLKX2
output
Cycle time, ACLKR2 internal, ACLKR2 output
Cycle time, ACLKR2 external, ACLKR2 output
Cycle time, ACLKX2 internal, ACLKX2 output
Cycle time, ACLKX2 external, ACLKX2 output
Pulse duration, ACLKR2 internal, ACLKR2 output
Pulse duration, ACLKR2 external, ACLKR2 output
Pulse duration, ACLKX2 internal, ACLKX2 output
Pulse duration, ACLKX2 external, ACLKX2 output
Delay time, ACLKR2 internal, AFSR output(7)
Delay time, ACLKX2 internal, AFSR output(8)
Delay time, ACLKX2 internal, AFSX output
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
11
12
tc(ACLKRX)
ns
ns
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
tw(ACLKRX)
-1.4
-1.4
-1.4
2.9
2.8
2.8
2.8
10
Delay time, ACLKR2 external input, AFSR output(7)
Delay time, ACLKX2 external input, AFSR output(8)
Delay time, ACLKX2 external input, AFSX output
2.9
10
13
td(ACLKRX-AFSRX)
ns
2.9
10
Delay time, ACLKR2 external output, AFSR
output(7)
2.9
2.9
10
10
Delay time, ACLKX2 external output, AFSR
output(8)
Delay time, ACLKX2 external output, AFSX output
Delay time, ACLKX2 internal, AXR2[n] output
Delay time, ACLKX2 external input, AXR2[n] output
2.9
-1.4
2.9
10
2.8
10
14
15
td(ACLKX-AXRV)
ns
ns
Delay time, ACLKX2 external output, AXR2[n]
output
2.9
-1.4
2.9
10
2.8
10
Disable time, ACLKX2 internal, AXR2[n] output
Disable time, ACLKX2 external input, AXR2[n]
output
tdis(ACLKX-AXRHZ)
Disable time, ACLKX2 external output, AXR2[n]
output
2.9
10
(1) McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR2.
(3) AHX - Cycle time, AHCLKX2.
(4) P = SYSCLK2 period
(5) AR - ACLKR2 period.
(6) AX - ACLKX2 period.
(7) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(8) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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Peripheral Information and Electrical Specifications
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