OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-23. EMIFB Base Controller Registers
BYTE ADDRESS
Acronym
MIDR
Register
0xB000 0000
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
Module ID Register
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
PC1
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
Performance Counter 1 Register
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PC2
PCC
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
Interrupt Mask Set Register
IMCR
Interrupt Mask Clear Register
6.11.2 EMIFB Electrical Data/Timing
Table 6-24. EMIFB SDRAM Interface Timing Requirements
NO.
MIN
MAX UNIT
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK
rising
19
tsu(EMA_DV-EM_CLKH)
th(CLKH-DIV)
0.5
ns
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK
rising
20
1.5
ns
Table 6-25. EMIFB SDRAM Interface Switching Characteristics
NO.
1
PARAMETER
MIN
7.5
3
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMB_CLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
5.1 ns
ns
4
0.9
0.9
5
5.1 ns
ns
6
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0]
valid
7
8
td(CLKH-AV)
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] invalid
toh(CLKH-AIV)
0.9
9
td(CLKH-DV)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
5.1 ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
0.9
0.9
0.9
0.9
0.9
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
5.1 ns
ns
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Peripheral Information and Electrical Specifications
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