OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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6.12.3 MMC/SD Electrical Data/Timing
Table 6-27. Timing Requirements for MMC/SD Module
(see Figure 6-26 and Figure 6-28)
NO.
1
MIN
TBD
MAX
UNIT
ns
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, SD_CMD valid before SD_CLK high
2
Hold time, SD_CMD valid after SD_CLK high
Setup time, SD_DATx valid before SD_CLK high
Hold time, SD_DATx valid after SD_CLK high
TBD
TBD
TBD
ns
3
ns
4
ns
Table 6-28. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-25 through Figure 6-28)
NO.
7
PARAMETER
Operating frequency, SD_CLK
MIN
MAX
UNIT
f(CLK)
TBD
TBD
TBD
TBD
TBD MHz
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
Identification mode frequency, SD_CLK
Pulse width, SD_CLK low
TBD KHz
9
ns
ns
10
11
12
13
14
Pulse width, SD_CLK high
Rise time, SD_CLK
TBD
TBD
TBD
TBD
ns
ns
ns
ns
tf(CLK)
Fall time, SD_CLK
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, SD_CLK low to SD_CMD transition
Delay time, SD_CLK low to SD_DATx transition
TBD
TBD
10
9
7
MMCSD_CLK
MMCSD_CMD
13
13
13
13
START
XMIT
Valid
Valid
Valid
END
Figure 6-25. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 6-26. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 6-27. MMC/SD Host Write Timing
120
Peripheral Information and Electrical Specifications
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