XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-78. Bit Descriptions – Link Control Register (continued)
BIT
3
FIELD NAME
RCB
ACCESS
DESCRIPTION
Read completion boundary. This bit specifies the minimum size read completion packet that the
XIO3130 can send when breaking a read request into multiple completion packets. This field is
not applicable to XIO3130; i.e., the XIO3130 does not break up completion packets and is
hardwired to zero.
r
r
0 – 64 bytes
1 – 128 bytes
2
RSVD
Reserved. When read, this bit returns zero.
Active State Link PM Control. This field is used to enable and disable active state PM.
00 – Active State PM disabled
1:0
ASLPMC
rw
01 – L0s entry enabled
10 – Reserved
11 – L0s and L1 entry enabled
4.3.54 Link Status Register
The Link Status register indicates the current state of the PCI Express Link.
PCI register offset:
Register type:
A2h
Read Only; Hardware Update
XX11h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
x
0
0
0
0
0
1
0
0
0
1
Table 4-79. Bit Descriptions – Link Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:14
RSVD
r
Reserved. When read, these bits return zeros.
Data link layer active. When the DLL_LARC field in the Link Capabilities register is asserted,
this field returns the value of the following comparison: (Link_State == DL_Active). This field
returns zero when the DLL_LARC field in the Link Capabilities register is de-asserted.
13
DLL_ACTV
r
Slot clock configuration. This bit reflects the reference clock configurations and is read-only 1,
indicating that a 100 MHz common clock reference is used.
12
11
SCC
LT
r
Link training in progress. The hardware automatically clears this bit when the LTSSM exits the
Configuration/Recovery state.
ru
10
9:4
3:0
UNDEF
NLW
LS
r
r
r
Undefined. The value read from this bit is undefined.
Negotiated link width. This field is read-only 000001b, which indicates that the lane width is x1.
Link speed. This field is read-only 0001b, which indicates that the link speed is 2.5 Gb/s.
4.3.55 Slot Capabilities Register
The Slot Capabilities register indicates the slot-specific capabilities of the downstream port.
PCI register offset:
Register type:
A4h
Read/Write; Read Only; Hardware Update
0000 0060h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
112
XIO3130 Configuration Register Space
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