ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
0
1: Output
P3DIR.x
Direction Control
1
0
1
From Module
Pad Logic
P3.0/STE0
P3OUT.x
Module X OUT
P3.4/UTXD0
P3.5/URXD0
‡
P3.6/UTXD1
P3.7/URXD1
¶
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
DIRECTION
PnSel.x
PnDIR.x
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
DV
PnIN.x
MODULE X IN
P3Sel.0
P3Sel.4
P3Sel.5
P3Sel.6
P3Sel.7
P3DIR.0
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
DV
DV
DV
DV
DV
P3OUT.0
P3OUT.4
P3OUT.5
P3OUT.6
P3OUT.7
P3IN.0
P3IN.4
P3IN.5
P3IN.6
P3IN.7
STE0
SS
CC
SS
CC
SS
SS
†
UTXD0
DV
Unused
§
URXD0
Unused
SS
UTXD1
‡
¶
URXD1
DV
SS
†
‡
§
¶
Output from USART0 module
Output from USART1 module in x14x(1) configuration, DV
Input to USART0 module
in x13x configuration
SS
Input to USART1 module in x14x(1) configuration, unused in x13x configuration
44
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